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rev. 0.5 7/12 copyright ? 2012 by silicon laboratories c8051t620/2-dk c8051t620/2-dk c8051t620/2 d evelopment k it u ser ? s g uide 1. kit contents the c8051t620 and c8051t622 development kits contain the following items: ?? c8051t62x motherboard ?? c8051t62x emulation daughter board with c8051f34a installed ?? socket daughter board (one of the following): ?? c8051t620dk: c8051t62x qfn 32-pin ?? c8051t622dk: c8051t622 qfn 24-pin ?? device samples (one of the following): ?? c8051t620dk: c8051t620-gm (qty: 10) and c8051t626-b-gm (qty: 10) ?? c8051t622dk: c8051t622-gm (qty: 10) ?? c8051txxx development kit quick-start guide ?? quick start guide includes steps to download the follo wing development software and documentation (these instructions can also be found in this document. see ?4. software installation? on page 3.): ? silicon laboratories integrated development environment (ide) ? evaluation version of 8051 development tools (macro assembler, linker, c compiler) ? source code examples and register definition files ? documentation ?? ac-to-dc universal power adapter ?? two usb cables 2. about the daughter boards the c8051t620 and c8051t622 development kits include an emulation daughter board (edb) and a qfn socket daughter board (qfn-db). the edb has an installed c8051f34a device, which is a flash-based device that can be used for the majority of c8051t62x/32x code development. the qfn-db is intended to allow both programming and system-level debugging of c8051t62x/32x devices directly. a c8051t62x/32x device cannot be erased once it ha s been programmed; so, it is advisable to use the c8051f34a for the majority of code development. refer to ?an368: differences between the c8051f34a and the c8051t62x and c8051t32x devi ce families? for more details on how t he c8051f34a can be used to develop code for the c8051t62x/32x device families. application notes can be found on the silicon labs web site: www.silabs.com/appnotes
c8051t620/2-dk 2 rev. 0.5 3. hardware setup see figure 1 for a diagram of the hardware configuration. 1. attach the desired daughter board to th e motherboard at connectors p1 and p2. 2. if using the qfn socket daughter board, place the device to be programmed into the socket. 3. place shorting blocks on j7 and the +3vd-vdd_pwr jumper pair on j6, as shown in figure 1. 4. connect the motherboard?s p5 usb connector to a pc running the silicon laboratories ide using the usb cable. 5. connect the ac-to-dc power adapter to connector p3 on the motherboard. notes: 1. use the reset icon in the ide to reset the target when connected during a debug session. 2. remove power from the motherboard and remove the u sb cable before removing a daughter board from the motherboard. connecting or disconnecting a daughter board when the power adapter or usb cable are connected can damage the motherboard, the daughter board, or the socketed device. 3. remove power from the motherboard and remove the usb c able before removing a c8051t62x/32x device from the socket. inserting or re moving a device from the socket when the po wer adapter or usb cable are connected can damage the motherboard, the daughter board, or the socketed device. 4. the above hardware setup instructions configure the de velopment system to be powered through the onboard 3.3 v regulator. for other power options, see "7.3. power supply headers (j6 and j7)" on page 15. figure 1. hardware setup (emulation daughter board) p3 silicon labs www.silabs.com reset j15 j7 usb active j5 j14 sw1 j12 j13 j1 debug pwr run vdd_pwr vdd_pwr vdd_pwr vdd_pwr +3vd vdd_ext vdd_debug vdd_comm j6 p2 p1 j2 sw2 j3 j4 usb active led1 pwr d10 d11 d12 r8 u2 cp2103 u1 f326 stop led1 j10 p2.2 p0.6 led2 p2.3 p1.2 sw1 j9 p2.0 p0.1 sw2 p2.1 p1.0 c8051t62x-mb led2 vpp p5 p4 j8 cts_debug p1.1 p1.2 rts_comm cts_comm rts_debug j11 tx_debug p0.4 p0.5 rx_comm tx_comm rx_debug j1 ac adapter usb cable place shorting blocks on j7 and j6 as shown. u1 f34a vregin vregin vbus vdd p3 silicon labs www.silabs.com c8051t62x edb
c8051t620/2-dk rev. 0.5 3 4. software installation all the latest software tools and do cumentation can be downloaded from www.silabs.com/mcudownloads . the silicon labs 8-bit development to ols download package available on th at web page includes the silicon laboratories integrated development environment (ide), 8051 evaluation toolset, virtual com port drivers for the cp210x usb to uart bridge, and additional documentation. download the package and install the components by following the on-screen instructions. 4.1. system requirements the following are the system requirements necessary to run the debug and programming tools: ?? pentium-class host pc running microsoft windows 2000 or newer. ?? one available usb port. 4.2. development tools installation to install the ide, utilit ies, and code examples, perform the following steps: 1. run the silicon labs 8- bit development tools in staller downloaded from www.silabs.com/mcudownloads . 2. in the screen titled ?select installa tion packages?, the silicon labs ide, 8051 evaluation t oolset and cp210x virtual com port drivers will be che cked by default. the programs nece ssary to download and debug on the mcu are the silicon labs ide and the 8051 evaluation toolset. the cp210x drivers are necessary to use the uart capabilities of the target board. see ?4.3. cp2 10x usb to uart vcp driver installation ? for more information abou t installing the cp210x drivers. see ?5. software overview? for an overview of all applicable software included in the web download. 3. installers selected in step 3 will execute in sequen ce, prompting the user as they install programs, documentation, and drivers. 4.3. cp210x usb to uart vcp driver installation the c8051t62x motherboard includes a silicon laboratories cp2103 u sb-to-uart bridge controller. device drivers for the cp2103 need to be installed before pc so ftware, such as hyperterminal, can communicate with the board over the usb conn ection. if the ?install cp210x drivers? option was selected during installation, this will launch a driver ?unpacker? utility. 1. follow the steps to copy the dr iver files to the desired location. the default directory is c:\silabs\mcu\cp210x . 2. the final window of this installer wi ll provide an option to install the driver on the target system. select the ?launch the cp210x vcp driver installe r? option in that window if you are ready to install the driver. you do not need to have the motherboard's usb connector pl ugged into the pc's usb port for this step. 3. if selected, the driver installer will now launch, providing an option to specify the driver installation location. after pressing the ?install? button, the installer will search your system for copi es of previously installed cp210x virtual com port drivers. it will let you know when your system is up-to-date. the driver files included in this installation have been certified by microsoft. 4. if the ?launch the cp210x vcp driver installer? option was not selected in step 3, the installer can be found in the location specified in step 2 (by default, c:\silabs\mcu\cp210x\windows ). at this location, run cp210xvcpinstaller.exe . 5. to complete the installation process, connect the included usb cable between t he host computer and the comm usb connector (p4) on the c8051t62x motherboard. windows will automatically finish the driver installation. information windows will pop up from the ta skbar to show the installation progress. 6. if needed, the driver files can be un installed by selecting the ?silicon labo ratories cp210x usb to uart bridge (driver removal)? option in the ?add or remove programs? window.
c8051t620/2-dk 4 rev. 0.5 5. software overview the following software is necessary to build a project, download code to, and communicate with the target microcontroller. ?? 8051 evaluation toolset ?? silicon labs integrated de velopment environment (ide) other useful soft ware included in the silicon labs 8-bit de velopment tools package from the silicon labs downloads web site ( www.silabs.com/mcudownloads ) includes: ?? configuration wizard 2 ?? keil vision2, vision3, and vision4 drivers ?? mcu production programmer a nd flash programming utilities 5.1. 8051 evaluation toolset the silicon labs ide has native suppor t for many third-party 8051 toolsets . included with this kit is an 8051 evaluation assembler, compiler, and lin ker. for further information on the tools, including limitations, see the corresponding application note. application notes can be found on the s ilicon labs web site ( http:// www.silabs.com/appnotes ). see table 1 for a list of supported t oolsets and associat ed application notes. 5.2. silicon labs ide the silicon labs ide integrates a s ource-code editor, source-level deb ugger, and in-system programmer. the following sections discuss how to open an example project in the ide, build the source code, and download it to the target device. 5.2.1. running the t620_blinky or t622_blinky example program the t620_blinky or t622_blinky example program blinks an led on the target board. 1. open the silicon labs ide from the start menu. 2. select project ? open project to open an existing project. 3. browse to the c:\silabs\mcu\examples\c8051t620_1_6_7 _t320_3\blinky or silabs\mcu\exam- ples\c8051t622_3_t326_7\blinky directory (default) and select the t620_blinky_c.wsp or t622_blinky_c.wsp project file. click open . 4. once the project is open, build the project by clicking on the build/make project button in the toolbar or selecting project ? build/make project from the menu. note: after the project has been built the first time, the build/make project command will only build the files that have been changed since the previous build . to rebuild all files and project dependencies, click on the rebuild all button in the toolbar or select project ? rebuild all from the menu. 5. before connecting to the target device, several co nnection options may need to be set. open the connec- tion options window by selecting options ? connection options... in the ide menu. first, select the ?usb debug adapter? option. next, the correct ?de bug interface? must be selected. c8051t62x/32x devices use silicon labs ?c2? 2-wi re debug interface. on ce all the selections are made, click the ok but- ton to close the window. table 1. supported third party 8051 toolsets toolset application note keil ?an104: integrating keil 8051 tools into the silicon labs ide? raisonance ?an125: integrat ing raisonance 8051 tools into the silicon labs ide? tasking ?an126: integrating tasking 8051 tools into the silicon labs ide? hi-tech ?an140: integrating hi-tech 8051 tools into the silicon labs ide? sdcc ?an198: integrating sdcc 8051 tools into the silicon labs ide? iar ?an236: integrati ng iar 8051 tools into the silicon labs ide?
c8051t620/2-dk rev. 0.5 5 6. click the connect button in the toolbar or select debug ? connect from the menu to connect to the device. 7. download the project to the target by clicking the download code button in the toolbar. note: to enable automatic downloading if the program build is successful, select enable automatic con- nect/download after build in the project ? target build configuration dialog. if errors occur during the build process, the ide will not attempt the download. 8. click on the go button (green circle) in the toolbar or by selecting debug ? go from the menu to start run- ning the firmware. the led on the target board will start blinking. 5.2.2. creating a new project use the following steps to create a new project. once steps 1?5 in this section are complete, continue with step 3 from section 5.2.1. 1. select project ? new project to open a new project and reset all configuration settings to default. 2. select file ? new file to open an editor window. create your source file(s) and save the file(s) with a rec- ognized extension, such as .c, .h, or .asm, to enable color syntax highlighting. 3. right-click on ?new project? in the project window. select add files to project . select files in the file browser and click open . continue adding files until all project files have been added. 4. for each of the files in the projec t window that you want assembled, compiled, and linked into the target build, right-click on th e file name and select add file to build . each file will be as sembled or compiled as appropriate (based on file extension) and linke d into the build of the absolute object file. note: if a project contains a large number of files, th e ?group? feature of the ide can be used to organize. right-click on ?new project? in the project window. select add groups to project . add predefined groups or add customized groups. right-click on the group name and choose add file to group . select files to be added. continue adding files until all project files have been added. 5. save the project when finished with the debug session to preserve the current target build configuration, editor settings, and the location of all open debug views. to save the project, select project ? save proj- ect as... from the menu. create a new name for the project and click on save .
c8051t620/2-dk 6 rev. 0.5 5.3. configuration wizard 2 configuration wizard 2 is a code genera tion tool for all silicon laboratories de vices. code is gen erated through the use of dialog boxes for each device peripheral as shown in figure 2. figure 2. configuration wizard 2 utility the configuration wizard utility helps accelerate deve lopment by automati cally generating initialization source code to configure and enable the on-chip resources needed by most design projects. in just a few steps, the wizard creates complete startup code for a sp ecific silicon laboratories mcu. the pr ogram is configurabl e to provide the output in c or assembly language. for more information, refer to the configuration wizard 2 help available under the help menu in configuration wizard 2 or refer to the configuration wizard 2 document ation. documentation and software are available from the downloads webpage: www.silabs.com/mcudownloads . 5.4. keil uvision2, uvision3, and uvision4 silicon la boratories drivers as an alternative to the silicon labor atories ide, the vision debug driver allows the keil vision2, vision3, and vision4 ides to communicate with silicon laboratories? on-chip debug logic. in-system flash memory programming integrated into the driver allows for rapid updating of target code. the vision2, vision3, and vision4 ides can be used to start and stop program ex ecution, set breakpoints, check variables, inspect and modify memory contents, and single-step through programs running on the actual target hardware. for more information, refer to the vision driver docu mentation. the documentation and software are available from the downloads webpage: www.silabs.com/mcudownloads .
c8051t620/2-dk rev. 0.5 7 5.5. programming utilities the silicon labs ide is the primary tool for downloadi ng firmware to the mcu during development. there are two software programming tools that are intended for use du ring prototyping or in the field: the mcu production programmer and the flash programming utilities. the mcu production programmer is installed with the ide to the directory, c:\silabs\mcu\utilities\prod uction programmer\ (default). t he flash programming utilities can be optionally installed from the web in staller, and are installed to c:\s ilabs\mcu\utilities\fl ash programming\ (default). 5.6. toolstick terminal the onboard debug circuitry provides both an in -system programming and debugging interface and a communications interface to the target microcontroller' s uart. the toolstick terminal software can access the debug hardware's communications path and provides a te rminal-like interface on the pc. note that for concurrent debugging and uart communications, the cp2103 usb-to-uart bridge is also included onboard. in addition to the standard terminal functions (send file , receive file, change baud rate), two gpio pins on the target microcontroller can be controlled using the te rminal for either rts/cts handshaking or software- configurable purposes. the toolstick terminal software is available on the downloads webpage: www.silabs.com/ mcudownloads .
c8051t620/2-dk 8 rev. 0.5 6. exampl e source code example source code and register definitio n files are provided by default in the silabs\mcu\examples\c8051t620_1_6_7_t320_3 or silabs\mcu\examples\c8051t622_3_t326_7 directory during ide installation. these files may be used as a template for code development. 6.1. register definition files register definition files c8051t620.inc , c8051t622.inc , c8051t620_defs.h , c8051t622_defs.h , and compiler_defs.h define all sfr registers and bit-addressable contro l/status bits. they are installed by default into the silabs\mcu\examples\c8051t620_1_6_7_t320_3 or silabs\mcu\examples\c8051t622_3_t326_7 directory during ide installation. the register and bit nam es are identical to those used in the c8051t620-21-26- 27_t320-3 or c8051t622-23_t326-27 data sheet. 6.2. blinking led example the example source files t620_blinky.asm and t620_blinky.c or t622_blinky.asm and t622_blinky.c show examples of several basic c8051t62x functions. these include disabling the watchdog timer (wdt), configuring the port i/o crossbar, configuring a timer for an interrup t routine, initializing the syst em clock, and configuring a gpio port. when compiled/assembled and linked, thes e programs flash the green led on the c8051t62x motherboard about five times a second using the interrupt handler with a timer.
c8051t620/2-dk rev. 0.5 9 7. development boards the c8051t620/2 development kit includes a motherboard that interfaces to various daughter boards. the c8051t62x emulation daughter board contains a c8051f34a device to be used for preliminary software development. the c8051t620 socket daughter board and c8051t622 socket daughter board allow programming and evaluation of the ac tual c8051t62x devices. numerous input/output (i/o) connections are provided on the mother board to facilitate prototypin g. figure 3 shows the c8051t62x motherboard and indicates locations for various i/o connectors. figure 4 shows the fact ory default shorting block positions. figures 5, 6, and 7 show the available c8051t62x daughter boards. figures 8, 9, 10, and 11 show the available c8051t32x daughter boards. ?? p1, p2 daughter board connection ?? p3 power connector that accepts input from 7.5 to 15 v dc unregulated power adapter ?? p4 usb connector for uart to usb communications interface ?? p5 usb debug interface connector ?? j1 analog i/o terminal block ?? j2 port 0 header ?? j3 port 1 header ?? j4 port 2 header ?? j5 port 3 header with access to vdd and gnd ?? j6 power supply selection header (see "7.3. power supply headers (j6 and j7)" on page 15) ?? j7 power supply enable header that connects power source selected on j6 to the board's main power supply net ?? j8 communications interface control signal header ?? j9 connects port pins to the switches labeled ?sw1? and ?sw2? ?? j10 connects port pins to the leds labeled ?led1? and ?led2? ?? j11 communications interface data signal header ?? j12 connects potentiometer to the port pin, p2.5 ?? j13 additional connections to ground ?? j14 connects an external vref from j1 to p0.7 ?? j15 vpp supply connection used when programming eprom devices
c8051t620/2-dk 10 rev. 0.5 figure 3. c8051t62x motherboard figure 4. c8051t62x motherboard default shorting block positions p3 silicon labs www.silabs.com reset j15 j7 usb active j5 j14 sw1 j12 j13 j1 debug pwr run vdd_pwr vdd_pwr vdd_pwr vdd_pwr +3vd vdd_ext vdd_debug vdd_comm j6 p2 p1 j2 sw2 j3 j4 usb active led1 pwr d10 d11 d12 r8 u2 cp2103 u1 f326 stop led1 j10 p2.2 p0.6 led2 p2.3 p1.2 sw1 j9 p2.0 p0.1 sw2 p2.1 p1.0 c8051t62x-mb led2 vpp p5 p4 j8 cts_debug p1.1 p1.2 rts_comm cts_comm rts_debug j11 tx_debug p0.4 p0.5 rx_comm tx_comm rx_debug p3 silicon labs www.silabs.com reset j15 j7 usb active j5 j14 sw1 j12 j13 j1 debug pwr run vdd_pwr vdd_pwr vdd_pwr vdd_pwr +3vd vdd_ext vdd_debug vdd_comm j6 p2 p1 j2 sw2 j3 j4 usb active led1 pwr d10 d11 d12 r8 u2 cp2103 u1 f326 stop led1 j10 p2.2 p0.6 led2 p2.3 p1.2 sw1 j9 p2.0 p0.1 sw2 p2.1 p1.0 c8051t62x-mb led2 vpp p5 p4 j8 cts_debug p1.1 p1.2 rts_comm cts_comm rts_debug j11 tx_debug p0.4 p0.5 rx_comm tx_comm rx_debug
c8051t620/2-dk rev. 0.5 11 figure 5. c8051t62x emulation daughter board figure 6. c8051t620 qfn32 socket daughter board figure 7. c8051t622 qfn24 socket daughter board u1 f34a vregin vregin vbus vdd p3 silicon labs www.silabs.com c8051t62x edb j1 vbus vregin vdd vregin p3 vio vdd j2 c8051t62x qfn32 skt db silicon labs www.silabs.com j3 j1 vbus vregin vdd vregin silicon labs www.silabs.com p3 vio vdd j2 c8051t622 qfn24 skt db j3
c8051t620/2-dk 12 rev. 0.5 figure 8. c8051t320 qfp32 socket daughter board figure 9. c8051t321 qfn28 socket daughter board figure 10. c8051t326 qfn28 socket daughter board j1 vbus vregin vdd vregin silicon labs www.silabs.com p3 j2 c8051t320 qfp32 skt db j1 vbus vregin vdd vregin silicon labs www.silabs.com p3 j2 c8051t321 qfn28 skt db j1 vbus vregin vdd vregin silicon labs www.silabs.com p3 vio vdd j2 c8051t326 qfn28 skt db j3
c8051t620/2-dk rev. 0.5 13 figure 11. c8051t327 qfn28 socket daughter board j1 vbus vregin vdd vregin silicon labs www.silabs.com p3 c8051t327 qfn28 skt db j3
c8051t620/2-dk 14 rev. 0.5 7.1. system clock sources the c8051t62x/32x devices feat ure a calibrated intern al oscillator that is enabled as the system clock source on reset. after reset, the intern al oscillator operates at a frequency of 48 mhz (1. 5%) by default but may be configured by software to operate at other frequencies. ther efore, in many app lications, an external oscillator is not required. however, if you wish to operate the c8051t62x/32x device at a frequency not available with the internal oscillator, an external oscillator so urce may be used. refer to the c805 1t620-21-26-27_t320 -3 or c8051t622- 23_t326-27 data sheet for more information on configuring the system clock source. 7.2. switches, leds, and po tentiometer (j9, j10, and j12) three switches are provided on the motherboard. the reset switch is connected to the rst pin of the c8051t62x/32x. pressing reset puts th e device into its hardwa re-reset state. the switch labeled ?sw1? can be connected to the c8051t62x/32x's general-purpose i/o (g pio) pins p0.1 and p2.0, and ?sw2? can be connected to the c8051t62x/32x's general-purpos e i/o (gpio) pins p1.0 and p2.1 through header j9. pressing a switch generates a logic low signal on the port pin. remove its sh orting block from the j9 header to disconnect the switch from the port pin. seven leds are also provided on the motherboard. the red led labeled ?pwr? (d4) is used to indicate a power connection to the motherboard. the green led labeled ?r un? (d10) turns on when the debug circuitry is in a running state; the red led labeled ?stop? (d11) turns on wh en the debug circuitry is in a halted state, and the orange led labeled ?debug pwr? (d12) indicates whet her the debug adapter circuit is being powered through p5's usb connector. the red led labeled ?vpp? (d7) indica tes when the vpp pr ogramming voltage is being applied to the device. the green leds, labeled ?led1? (d1) and ?led2? (d2), can be connected to c8051t62x/ 32x's gpio pins through header j10. remove its shorting block from the header to disconnect an led from the port pin. the red led labeled ?usb active? (d13) will turn on whenever the cp2103 usb-to-uart bridge is connected to a pc and has successfully completed enumeration. also included on the c8051t62x motherboard is a 10 k ? thumbwheel rotary potentiometer, reference number r8. the potentiometer can be connected to the c8051t62x/3 2x's p2.5 pin through the j12 header. remove the shorting block from the header to disconnect the potentiometer from the port pin.
c8051t620/2-dk rev. 0.5 15 table 2 lists the port pins and headers correspo nding to the switches, leds, and potentiometer. 7.3. power supply headers (j6 and j7) the main power supply of the motherboar d, which is used to power the daught er board, can be provided by either the usb debug adapter?s on-chip voltage regulator, the cp2103 usb-to-uart bridge?s on-chip voltage regulator, p3 and its associated circuitry, or an external voltage applied to the vdd_ext connection on j1. to select a power supply, place a shorting block on j6 across the appropria te pin pair, as shown in figure 12. to connect the main power supply to an attached daughter bo ard, place a shorting block across j7. notes: 1. only one shorting block should be placed on j6 at a time. 2. to use the cp2103?s voltage regulator as the board's power s upply, a usb cable must be connected to p4, and the usb active led (d2) must be on. 3. to use the usb debug adapter?s voltage regulator as the board's power supply, a usb cable must be connected to p5, and the debug pwr led (d12) must be on. figure 12. j6 and j7 shorting block configuration for power options table 2. motherboard i/o descriptions description component name i/o header switch sw1 daughte r card's p0.1 daughter card?s p2.0 j9 [2-4] j9 [4-6] switch sw2 daughter card?s p1.0 daughter card?s p2.1 j9 [1-3] j9 [3-5] reset sw3 daughter card's rst/c2ck none green led labeled ?led1? d1 daughter card's p0.6 daughter card's p2.2 j10 [2-4] j10 [4-6] green led labeled ?led2? d2 daughter card?s p1.2 daughter card's p2.3 j10 [1-3] j10 [3-5] red led labeled ?pwr? d4 dau ghter card's vdd j6, j7 red led labeled ?vpp? d7 da ughter card's vpp pin (see "vpp pin sharing" on page 17) j15 green led labeled ?run? d10 debug adapter signal none red led labeled ?stop? d11 debug adapter signal none orange led labeled ?debug pwr? d12 debug adapter signal none green led labeled ?usb active? d13 u2 cp2103's suspend none potentiometer r8 daugh ter card's p2.5 j12 j7 j6 vdd_pwr +3vd vdd_ext vdd_debug vdd_comm j7 j6 vdd_pwr +3vd vdd_ext vdd_debug vdd_comm j7 j6 vdd_pwr +3vd vdd_ext vdd_debug vdd_comm j7 j6 vdd_pwr +3vd vdd_ext vdd_debug vdd_comm +3.3v regulator power (from p3) cp2103 regulator power (from usb at p4) debug circuit power (from usb at p5) external power source (from j1 connector) vdd_pwr vdd_pwr vdd_pwr vdd_pwr vdd_t620 vdd_t620 vdd_t620 vdd_t620
c8051t620/2-dk 16 rev. 0.5 7.4. usb debug adapter (debug/p5) a universal serial bus (usb) connector (p5) provides the onboard debug and programming interface. the debug/ programming mcu and associated circuitry are powered through the usb connector, which can also supply the rest of the motherboard by routing the usb debug ad apter's power through j6. the usb debug adapter also provides a data communications interface that c an be used when the debug adapter is not debugging or programming a c8051t62x/32x device. 7.5. uart to usb communi cations interfaces (comm/p4) the c8051t62x motherboard provides uart to usb comm unications interfaces through both the cp2103 usb- to-uart bridge device and the communicati ons interface of the usb debug adapter. the cp2103 bridge device connects to a pc through the usb connector labeled ?comm? (p4). this usb connector supplies power to the cp2103 and can supply power to the rest of the motherboard by configuring j6 and j7 as shown in figure 12. to use the cp2103 as a communications interface, the cp2103 virtual com port drivers must be installed on a pc. the usb debug adapter's communications interface c onnects to a pc through p5. access to the usb debug adapter's communications interface is provided by th e windows program called ?toolstick terminal?, which is available for download for free from t he silicon laboratories website. see the toolstick terminal help file for information on how to use toolstick terminal. 7.6. communications interface selector headers (j8 and j11) the c8051t62x motherboard routes the c8051t62x/32x' s p0.4 (uart tx) and p0.5 (uart rx) to j11 where those signals can be connected to either the cp2103 usb-to-uart bridge or the usb debug adapter. the motherboard also allows the c8051t62x/32x's p1.1 and p1 .2 to be used as the uart control signals, cts and rts. these two signals are routed to j8, where they can be connected to either the cp2103 or the usb debug adapter. the jumper options for using either the cp2103 or t he debug adapter circuit for uart communications can be found in figure 13. figure 13. shorting block configuration for uart communication options 7.7. port i/o connect ors (j2, j3, j4, and j5) each of the c8051t62x/32x's i/o pins, as well as +3vd and gnd, are routed to headers j2 through j5. j2 connects to the microcontroller's port 0 pins; j3 connects to port 1; j4 connects to port 2, and j5 connects to port 3. cts_debug p1.1 p1.2 rts_comm cts_comm rts_debug j8 cts_debug p0.4 p0.5 rx_comm cts_comm rx_debug j11 cp2103 bridge (usb connection at p4) rts_debug p1.1 p1.2 rts_comm cts_comm rts_debug j8 tx_debug p0.4 p0.5 rx_comm tx_comm rx_debug j11 debug adapter comms (usb connection at p5)
c8051t620/2-dk rev. 0.5 17 7.8. analog i/o (j1 and j14) three of the c8051t62x/32x target device's port pins are connected to the j1 terminal block. the terminal block also allows users to input an external voltage that can be used as the power supply of the board. refer to table 3 for the j1 terminal block connections. placing a shorting block on j14 will connect the p0.7/vref signal on j1 to the p0.7 pin of the device. 7.9. vpp connection (j15) the c8051t62x/32x devices require an external 6.0 v programming voltage applied to the vpp pin during device programming. the vpp pin on these devi ces is shared with p1.5 or p1 .1 depending on th e device. during programming, the vpp voltage is automatically enabled when needed. head er j15 is provided to allow the user to disconnect the programming circuitry from the vpp pi n to avoid interfering with th e normal application operation of the gpio pin. when programming the device, j15 should be shorted with a shorting block. when running normal application code, j15 can be removed. see table 4 for more information on which port pins are shared with vpp. table 3. j1 terminal block descriptions pin # description 1v r e g i n 2v i o 3g n d 4 p2.5 (analog input) 5 p0.7/vref (routed to header j14) 6 vdd_ext (routed to header j6) table 4. vpp pin sharing device pin shared with vpp c8051t620 c8051t621 c8051t626 c8051t627 c8051t320 c8051t321 c8051t322 c8051t323 p1.5 c8051t622 c8051t623 c8051t326 c8051t327 p1.1
c8051t620/2-dk 18 rev. 0.5 7.10. using alternate supplies wi th the c8051t62x development kit for most evaluation purposes, the onboard 3.3 v supply regulator is sufficient to be used as a vdd power supply. however, in applications where a different supply voltage is desired (e.g., 1.8 v), an external supply voltage can be applied to the board at the analog connector (j1). some devices in the c8051t62x/32x family also support a separate voltage input for the input/output voltage of the port pins. this voltage input/output (vio) should be input to j1 on pin 2. see the c8051t620-21-26-27_t320-3 or c8051t622-23_t326-27 data sheet for more information about vio usage and constraints. notes: 1. when programming a c8051t62x/32x device, vdd must be at least 3.3 v. vdd can be supplied directly to the device, or the on-chip 5 v regulator can be used. 2. if an external supply voltage is desired, the shorting block on j6 should be placed so that the pin 3 (vdd_ext) is shorted to pin 4 (vdd_pwr).
c8051t620/2-dk rev. 0.5 19 8. schematics figure 14. c8051t62x motherboard schematic (1 of 2)
c8051t620/2-dk 20 rev. 0.5 figure 15. c8051t62x motherboard schematic (2 of 2)
c8051t620/2-dk rev. 0.5 21 figure 16. c8051t62x emulation daughter board schematic
c8051t620/2-dk 22 rev. 0.5 figure 17. c8051t620 qfn-32 daughter board schematic
c8051t620/2-dk rev. 0.5 23 figure 18. c8051t622 qfn-24 daughter board schematic
c8051t620/2-dk 24 rev. 0.5 figure 19. c8051t320 qfp-32 daughter board schematic
c8051t620/2-dk rev. 0.5 25 figure 20. c8051t321 qfn-28 daughter board schematic
c8051t620/2-dk 26 rev. 0.5 figure 21. c8051t326 qfn-28 daughter board schematic
c8051t620/2-dk rev. 0.5 27 figure 22. c8051t327 qfn-28 daughter board schematic
c8051t620/2-dk 28 rev. 0.5 d ocument c hange l ist revision 0.2 to revision 0.3 ?? updated "4.2. developmen t tools installation" on page 3. ?? updated "4.3. cp210x usb to uart vcp driver installation" on page 3. ?? updated figure 17 on page 22. ?? updated figure 18 on page 23. ?? updated figure on page 28. revision 0.3 to revision 0.4 ?? updated "1. kit contents" on page 1. ?? updated "2. about the daughter boards" on page 1. ?? updated "6. example source code" on page 8. ?? updated project paths ?? updated "7. development boards" on page 9. ?? updated "8. schematics" on page 19. ?? added figures 19, 20, 21, and 22. ?? updated c8051t62x references to include c8051t32x devices. ?? updated data sheet references. revision 0.4 to revision 0.5 ?? updated "1. kit contents" on page 1. ?? updated document to reflect change from cd- rom based installation to web-based installer. ?? updated various sections to include the new c8051t626/7 part numbers.
c8051t620/2-dk rev. 0.5 29 n otes :
c8051t620/2-dk 30 rev. 0.5 c ontact i nformation silicon laboratories inc. 400 west cesar chavez austin, tx 78701 tel: 1+(512) 416-8500 fax: 1+(512) 416-9669 toll free: 1+(877) 444-3032 please visit the silicon labs technical support web page: https://www.silabs.com/support/pages/contacttechnicalsupport.aspx and register to submit a technical support request. silicon laboratories and silicon labs are trademarks of silicon laboratories inc. other products or brandnames mentioned herein are trademarks or registered trademarks of their respective holders. the information in this document is believed to be accurate in all respects at the time of publ ication but is subject to change without notice. silicon laboratories assumes no responsibility for errors and omissions, and disclaims responsibi lity for any consequences resu lting from the use of information included herein. ad ditionally, silicon laboratorie s assumes no responsibility for the functioning of und escribed features or parameters. silicon laboratories reserves the right to make changes without further notice . silicon laboratories makes no wa rranty, rep- resentation or guarantee regarding the suitability of its products for any particular purpose, nor does silicon laboratories as sume any liability arising out of the application or use of any product or circuit, and s pecifically disclaims any and all liability, including wi thout limitation conse- quential or incidental damages. silicon laborat ories products are not designed, intended, or authorized for use in applications intended to support or sustain life, or for any other application in which the failure of t he silicon laboratories product could create a s ituation where per- sonal injury or death may occur. should buyer purchase or us e silicon laboratories products for any such unintended or unauthor ized ap- plication, buyer shall indemnify and hold silicon laboratories harmles s against all claims and damages.

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